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Freescale Semiconductor /MK61F15WS /DDR /CR48

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Interpret as CR48

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0P1PRIRLX0RESERVED0 (0000)P2PRI00RESERVED 0 (0000)P2PRI10RESERVED

P2PRI0=0000, P2PRI1=0000

Description

DDR Control Register 48

Fields

P1PRIRLX

Port 1 Priority Relax
RESERVED

Reserved
P2PRI0

Port 2 Priority 0 commands

0 (0000): Lowest

1 (0001): -----

14 (1110): -----

15 (1111): Highest
RESERVED

Reserved
P2PRI1

Port 2 Priority 1 commands

0 (0000): Lowest

1 (0001): -----

14 (1110): -----

15 (1111): Highest
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data